The present disclosure relates to a complementary metal oxide semiconductor (CMOS) image sensor and a fabrication method thereof. More particularly, a boundary region of a silicide barrier layer of a pixel region in a CMOS image sensor may be protected from wet etching by using a nitride layer. The performance of the CMOS image sensor may be improved, as well as the fabricating method thereof.
CMOS image sensors convert an optical signal into an electric signal. A CMOS image sensor includes a pixel region, which is responsive to an optical signal, and a periphery region, which is not responsive to an optical signal. The pixel region may be isolated from the periphery region by a device isolation region. The device isolation region may be formed using a shallow trench isolation (STI) process. In an STI process, a trench may be formed by etching a semiconductor substrate. The trench may be then filled with a dielectric material. The dielectric fill material may be planarized to form the device isolation region.
A silicide process in which metal atoms are diffused into a silicon substrate to reduce contact resistance may be used in the fabrication of the CMOS image sensor. The silicide may be formed in the periphery region, outside a pixel region in which electricity is generated by the photoelectric effect. Silicide formed in the pixel region may degrade light transmission characteristics and may cause junction leakage in the pixel region, thereby deteriorating electrical characteristics of the device.
FIGS. 1A to 1D are cross-sectional views illustrating a method for fabricating a related art CMOS image sensor. Referring to FIG. 1A, a nitride layer 130 to be used as a sidewall of a gate electrode is deposited over a semiconductor substrate. A photodiode 100, formed in an active region, includes implanted n-type impurity ions. In a remaining region outside the active region into which the n-type impurity ions are implanted, an additional impurity ion implantation process may be performed before or after the deposition of the nitride layer 130 by adjusting a corresponding photo masking process. A polyline 120 running over a shallow trench isolation (STI) 110 region is shown in FIG. 1A. The polyline 120 may be a select line connected to a select transistor among transistors constituting pixels of a CMOS image sensor.
A silicide barrier layer formed in a pixel region having the polyline 120 of the select transistor therebetween may have a minimized width. This minimized width may cause quality and yield issues related to a silicide barrier layer deposition process.
In FIG. 1B, the nitride layer may be etched across the surface without a masking process to form a spacer 130 of the polyline 120. In FIG. 1C, a silicide barrier layer 140 is deposited, a photoresist layer 150 is formed, and a photolithography process is performed. The silicide barrier layer 140 may be formed by depositing tetraethylorthosilicate (TEOS) oxide using a low pressure chemical vapor deposition (LPCVD) or a plasma enhanced chemical vapor deposition (PECVD). The photoresist 150 coated over the silicide barrier layer 140 may be formed to overlap the STI region 110 by 0.2 μm from a boundary between the STI region 110 and the pixel region 100.
Referring to FIG. 1D, the silicide barrier layer 140 of the STI region 110, which is not covered by the photoresist, may be removed by a wet etching process. The wet etching process may be selected because it may improve process yield and quality. A p-MOS transistor is relatively sensitive, and a dry-etching plasma may damage the pixel region of an image sensor.
After wet-etching, the silicide barrier layer over an edge portion 140a of the pixel region 100 may be extremely thin or completely removed. Therefore, the edge portion of the pixel region 100 may be silicided again during a subsequent silicide process.
To avoid this, the silicide barrier layer 140 of the pixel region 100 may protrude toward a periphery region adjacent to the pixel region. However, a portion to be silicided, such as the polyline 120 of the select transistor, may be blocked, resulting in a partial failure in the silicidation of the polyline 120. This may result in an error in forming an image.